Japanese Patent Application Laid-Open Publication No. 2011-134990 (Patent Document 1) describes a technique related to a semiconductor device which includes a microcomputer and a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In this technique, a wiring board is mounted on a chip mounting portion, and a semiconductor chip which composes the microcomputer is stacked and arranged on the wiring board.
Japanese Patent Application Laid-Open Publication No. H11-233712 (Patent Document 2) describes a technique related to an inverter mounting composition. More specifically, Patent Document 2 describes a technique of mounting, on a chip mounting portion, an IGBT chip having an IGBT (Insulated Gate Bipolar Transistor) formed thereon or a diode chip having a diode formed thereon, and mounting, on the wiring board, a control chip having a control circuit which controls an IGBT switching operation formed thereon, or a chip component (a passive component such as a gate resistance).
Japanese Patent Application Laid-Open Publication No. 2015-65339 (Patent Document 3) describes a technique of controlling six IGBTs by using two control ICs. That is, the Patent Document describes a technique of controlling three high-side IGBTs by a high-side control IC, and controlling three low-side IGBTs by a low-side control IC.